This invention relates to a half-tone mask, and more particularly to a method for fabricating a half-tone mask using, an electrolytic process which makes it possible to simplify the fabricating process.
In general, in order to fabricate chips, a plurality of chip regions are defined on a wafer using a stepping process. Then the chip regions are subjected to processes for many times.
However, in the stepping process in which a half-tone mask of a semitransparent material with a transmissivity of 4-10% is used, regions that have been multiply exposed can happen through the many times of exposure processes.
That is, even though the half-tone mask has a transmissivity of 4-10%, a light transmission through the mask having the transmissivity of, 8-20% for doubly exposed regions and 16-40% for four times exposed regions may expose the photoresist, resulting in the form of undesired patterns on the wafer.
Accordingly, to solve the aforementioned problem, a region that is not transmissive to lights is required on the half-tone mask, for which a guard-board is provided on at the periphery of a main chip with which multiple exposure can be prevented.
The guard-board of the conventional half-tone mask will be explained with reference to the attached drawing.
FIG. 1 illustrates a guard-board in the conventional half-tone mask, FIG. 2a is an enlarged sectional view of part "A" the guard-board of FIG. 7, FIG. 2b is an enlarged plan view of the guard-board of FIG. 1, and FIG. 2c is a detail view of part "B" of FIG. 2b.
As shown in FIG. 1, a conventional half-tone mask has the main chip 12 at the center, around which a guard-board region 13 is formed.
The region excluding the main chip 12 and the guard-board region 13 is an unnecessary region 11 in the mask.
The guard-board occupies an area of about 2.times.10.sup.8 .mu.m.sup.2 in the half-tone mask. As shown in FIG. 2a-2c, the guard-board has a shape of a checker board with a plurality of phase shift layers 20 each having a size of 1.0 .mu.m.times.1.0 .mu.m. That is, the guard-board is formed by using a method including the steps of forming a phased shift layer 20 of silicon oxide film(SiO.sub.2) or SOG(Spin On Glass) on a quartz substrate and forming a plurality of contact holes 20a each having a size of 1.0 .mu.m.times.1.0 .mu.m with a pitch of 1:1 in the phase shift layer 20.
However, the guard-board of the conventional half-tone mask has the following problems.
In general masks, contact holes of about 2.0 .mu.m.times.2.0 .mu.m size are used in fabrication of semiconductor devices.
However, the formation of the guard-board of the conventional half-tone mask requires formation of a plurality of contact holes each having a size of 1.0 .mu.m.times.1.0 .mu.m with a pitch of 1:1. The contact holes have to be formed an area of about 2.times.10.sup.8 .mu.m.sup.2 maintaining a size error within .+-.10%, which is a difficult process to carry out. As a result, productivity in mass production drops, causing mask costs to increase.